Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration
FASTER will facilitate the use of reconfigurable technology by providing a complete methodology that enables designers to easily implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology.
We expect that the project will lead to a 20% productivity improvement due to seamless implementation and verification of dynamically changing systems, a 50% total ownership cost reduction for NIDS and Reverse Time Migration systems, with a 2x performance improvement under power constraints for Global Illumination and Image Analysis.
R & D innovation
The R&D activities to be performed in FASTER are devoted to the development of novel techniques for optimizing and verifying static and dynamic aspects of a reconfigurable design, while minimizing run-time overheads on speed, area and power consumption. FASTER will also provide a powerful run-time system that will be able to run on multiple reconfigurable platforms and manage the various aspects of parallelism and adaptivity with reduced overhead.
Type:EU FP7 STREP
Duration:September 2011 – August 2014