Monthly Archives: September 2007

Paper: “A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip”

The paper “A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip”, authored by Giovanni Beltrame, Cristiana Bolchini, Luca Fossati, Antonio Miele e Donatella Sciuto has been presented at DFT 2007. Reliability issues play a relevant role in the design … Continue reading

Posted in Multichip Processor Architecture, Publications, Reliability, Simulation | Comments Off on Paper: “A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip”

Paper: “TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs”

The paper “TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs” authored by Cristiana Bolchini, Antonio Miele, Marco D. Santambrogio has been presented at DFT 2007. This paper presents the adoption of the Triple Modular Redundancy coupled with … Continue reading

Posted in Design Space Exploration, Dynamic Reconfiguration, Publications, Reliability | Comments Off on Paper: “TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs”