Monthly Archives: July 2007

Poster presentation: “Evolvable Hardware: a functional level evolution framework based on ImpulseC”

The short paper titled “Evolvable Hardware: a functional level evolution framework based on ImpulseC”, authored by Anna Antola, Marco Castagna, Pamela Gotti, David Pellerin, Marco D. Santambrogio has been presented at ERSA 2007.

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Poster presentation: “Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs”

The short paper titled “Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs”, authored by Cristiana Bolchini, Fabio Salice and Marco D. Santambrogio has been presented at ERSA 2007. This paper discusses innovative approaches to design digital systems on … Continue reading

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Conference: DFT 2007

22nd IEEE Intl Symp. on Defect and Fault Tolerance in VLSI Systems Sept. 26-28, 2007 Rome, Italy DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI systems inclusive … Continue reading

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