Category Archives: Reliability

Paper: “A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip”

The paper “A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip”, authored by Giovanni Beltrame, Cristiana Bolchini, Luca Fossati, Antonio Miele e Donatella Sciuto has been presented at DFT 2007. Reliability issues play a relevant role in the design … Continue reading

Posted in Multichip Processor Architecture, Publications, Reliability, Simulation | Comments Off on Paper: “A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip”

Paper: “TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs”

The paper “TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs” authored by Cristiana Bolchini, Antonio Miele, Marco D. Santambrogio has been presented at DFT 2007. This paper presents the adoption of the Triple Modular Redundancy coupled with … Continue reading

Posted in Design Space Exploration, Dynamic Reconfiguration, Publications, Reliability | Comments Off on Paper: “TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs”

Poster presentation: “Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs”

The short paper titled “Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs”, authored by Cristiana Bolchini, Fabio Salice and Marco D. Santambrogio has been presented at ERSA 2007. This paper discusses innovative approaches to design digital systems on … Continue reading

Posted in Dynamic Reconfiguration, Publications, Reliability | Comments Off on Poster presentation: “Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs”

Conference: DFT 2007

22nd IEEE Intl Symp. on Defect and Fault Tolerance in VLSI Systems Sept. 26-28, 2007 Rome, Italy DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI systems inclusive … Continue reading

Posted in Conferences, Reliability | Comments Off on Conference: DFT 2007

Paper: “SEU Mitigation for SRAM-Based FPGAs through Dynamic Partial Reconfiguration”

The paper titled “SEU Mitigation for SRAM-Based FPGAs through Dynamic Partial Reconfiguration”, authored by Cristiana Bolchini, Davide Quarta and Marco D. Santambrogio will be presented at the Great Lake Symposium on VLSI (GLSVLSI’2007). This paper presents a methodology for designing … Continue reading

Posted in Publications, Reliability | Comments Off on Paper: “SEU Mitigation for SRAM-Based FPGAs through Dynamic Partial Reconfiguration”