Category Archives: Dynamic Reconfiguration

Paper: “The Shining embedded system design methodology based on self dynamic reconfigurable architectures”

The short paper titled “The Shining embedded system design methodology based on self dynamic reconfigurable architectures”, authored by Marco D. Santambrogio, Carlo A. Curino, Vincenzo Rana, Francesco Redaelli and Donatella Sciuto will be presented at ASP-DAC 2008. Complex design, targeting … Continue reading

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Paper: “TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs”

The paper “TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs” authored by Cristiana Bolchini, Antonio Miele, Marco D. Santambrogio has been presented at DFT 2007. This paper presents the adoption of the Triple Modular Redundancy coupled with … Continue reading

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Poster presentation: “Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs”

The short paper titled “Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs”, authored by Cristiana Bolchini, Fabio Salice and Marco D. Santambrogio has been presented at ERSA 2007. This paper discusses innovative approaches to design digital systems on … Continue reading

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Paper: “Task Partitioning for the Scheduling on Reconfigurable Systems driven by Specification Self-Similarity”

The paper titled “Task Partitioning for the Scheduling on Reconfigurable Systems driven by Specification Self-Similarity ”, authored by Matteo Giani, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto has been be presented at ERSA 2007.

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Conference: ERSA 2007

The International Conference on Engineering of Reconfigurable Systems and Algorithms – ERSA June 25 – 28, 2007 Las Vegas, Nevada, USA ERSA conference is interested in all aspects of reconfigurable computing, including classical programmable logic, as well as configurable multiprogramming … Continue reading

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